1. Field
Example embodiments of the inventive concepts relate to semiconductor memory devices, and in particular, to data line layouts of conductive lines connected between I/O sense amplifiers and I/O pads in a semiconductor memory device.
2. Description of the Related Art
Semiconductor memory devices may include banks having a plurality of memory cells to improve data transmission rates and each bank may be divided into a plurality of DRAM array cell blocks. A bit line sense amplifier for controlling the input of data to each cell block or the output of data from each cell block may be connected to global input/output (I/O) lines through local I/O lines. The global I/O lines may be shared by all cell blocks of a corresponding bank and may be connected through a global I/O sense amplifier to data bus lines which may be shared by all banks. The data bus lines may be connected to corresponding data I/O pads.
Data bus lines are disposed in a peripheral region around a cell array region, resulting in long conductive paths. For this reason, it may be difficult to reduce the size of a chip and electrical characteristics may be degraded.